The present invention relates to simulation of fault-free and fault conditions of a circuit for evaluating circuit testing methods.
Over the past decade tremendous advances have been achieved in integrated circuit densities and the amount of logic that can be placed on a single integrated circuit chip. Accompanying these advances have been a series of improvements, albeit less dramatic ones, in the realm of printed circuit board (PCB) manufacture. Integrated circuit chip packaging techniques have been evolving constantly, with the goal of permitting more input/output pins on the chip package, and to allow an increasing number of chip packages to be mounted on a given board. As with chips, printed circuit boards contain far more logic today than they did 10 years ago. It is not uncommon today to squeeze all the logic for a powerful (even by today's standards) computer onto a PCB the size of a sheet of notebook paper.
One problem that results from the ever increasing density of chips and boards is the increased difficulty of test. As these entities become ever more dense, the task of determining whether or not they contain manufacturing or design defects becomes ever more difficult. Effective solutions to the problem may include several approaches, including the addition of logic to the design that is dedicated to test, and the use of sophisticated test equipment that provides improved visibility into the manufactured product. These approaches, while providing enhanced detection and diagnosis of design or manufacturing induced failures, are typically non-functional in nature. For printed circuit boards in particular, it is also desirable to perform a functional test prior to installing them in the final product. This functional test refers to operating the design in a manner that is consistent with how it will be operated in the final product by the end user. For instance, a central processing unit (CPU or, most commonly today, a microprocessor) would fetch instructions from memory, execute those instructions, and then perform a program to exercise the various subsystems that reside on the board. This type of test is a functional self-test (FST), since the product is testing itself in a functional mode.
One characteristic of FST that distinguishes it from other types of testing is that no external test equipment is being used to apply test vectors to the product. Typically, most printed circuit boards today undergo an in-circuit test, where a bed-of-nails test fixture is used to apply pre-computed test vectors to various points on the board. In this type of test, the vectors are stored in the tester and applied at a regular frequency until they have been exhausted. Likewise, the test equipment will be performing measurements at various points on the board at the same frequency. In a functional self-test, the test program is stored in ROM on the board itself, and the application of the test stimulus is via a microprocessor executing the program. Detection of defects occurs by the microprocessor interpreting the results of the executing program. It is key to note that defects occur at points in the program where the microprocessor is comparing expected results to actual results.
Regardless of the type of test being performed on the board (or chip or any product, for that matter), it is valuable to know the quality of the test. That is, what percentage of the potential defects will be exposed by the application of the test. We call this number test coverage. Obviously the higher the test coverage, the better; with 100% being the ultimate goal. A higher test coverage means a decreased chance that defective product will be delivered to the customer. Sometimes, particularly for chips and modules, a technique known as fault simulation is used to determine the test coverage number. This technique utilizes a simulation of the logic design, contained in software, wherein potential defects, or faults, are injected into the design and simulated in conjunction with the test stimuli to determine whether or not they are detected. The software program used to perform this analysis is called a fault simulator. Historically, there has been significant use of fault simulation for chip designs, but very limited use for printed circuit boards. Determination of test coverage for boards, if done at all, has tended to rely on manual insertion of faults onto a known good board.
There are several reasons for having to rely on the manual insertion of faults onto a known good board. The amount of logic contained on a printed circuit board is many times that contained on a single chip, since a PCB is composed of many chips. Fault simulation is an inherently compute intensive, time consuming task, thus frequently making the fault simulation of an entire PCB impractical. With ever more powerful computers, improved algorithms and new modelling techniques, these limitations are slowly giving way. Fault simulation of PCBs is still very time consuming, but has become possible with some constraints applied.
It has often been impossible to obtain software models of all the components that comprise a PCB. Most PCBs contain several off-the-shelf components for which the internal logic design is unavailable, often due to the fact that it is proprietary information of the manufacturer. Generating a software model for these components can be difficult and often impractical. Without such a model for every PCB component, a fault simulation is not very useful.
Today, there are companies whose sole business is the production of software models for a wide range of commercially available components. In addition, the advent of hardware modeling, wherein the actual component itself serves as a simulation model, has done much to relieve the problem. Dynamic hardware modellers, such as the series from Logic Modeling Corporation, can effectively support board fault simulation. Today, with some significant effort, one can typically find some means of constructing a complete model set for most PCBs.
Fault simulation has often been coupled with some form of automatic test generation. An automatic test generator (ATG) program develops test patterns to be applied to the unit under test, with the goal of achieving a high test coverage. The fault simulator grades the test patterns produced by the ATG, and indicates the test coverage. ATG programs can only function effectively on designs that have built-in testability structures (e.g., level sensitive scan design). While it is not uncommon for complex chips to have such structures, it is very unusual for an entire PCB to be designed in such a fashion. Thus the use of non-functional testing techniques, and the associated fault simulation, has been very limited at the board level.
This trend continues to be true today. Automatic test generation for general sequential circuitry remains poor, thus non-functional through-the-pins test of PCBs remains rare. There is a recently defined standard, IEEE 1149.1, that defines a set of testability structures and protocols, as boundary-scan, that does address non-functional testing at the board level. This type of testing should become more common over the next few years.
It is an object of the present invention to provide an apparatus and a method to determine the effectiveness of the test environment including devices external to the circuits under test such as logic analyzers and digital testers as well as devices contained in the circuits under test such as functional self-test code using fault simulation.
It is another object of the present invention to provide an apparatus and a method to determine the effectiveness of functional self-test code at detecting defects in populated printed circuit boards or printed circuit board designs using fault simulation.
It is yet another object of the present invention to provide apparatus and a method to predict circuit responses at monitoring points appropriate to the action and programming of the tester and other test conditions under fault-free and faulty conditions of the circuits under test using fault simulation.
It is a further object of the present invention to provide diagnostic data from the simulation of field testing procedures for use in failure isolation and circuit replacement in the field.
It is a still further object of the present invention to provide data that can be used for programming devices in the test environment.